Field of the Invention
The invention relates to a combined precharging and homogenizing circuit for a semiconductor memory configuration made up of a memory cell array having a multiplicity of bit line pairs. The combined precharging and homogenizing circuit contains a first and a second field-effect precharging transistor and a homogenizing transistor connected in series between the two precharging transistors. The gates of the two precharging transistors and of the homogenizing transistor are connected together to form a common gate. The sources of the precharging transistors are connected together to form a common source. The drain of the first precharging transistor and the drain of the homogenizing transistor are connected together to form a common drain and the source of the homogenizing transistor and the drain of the second precharging transistor are connected together to form a common source/drain.
Such a combined precharging and homogenizing circuit is used, among other things, to precharge the bit lines of DRAM memory configurations in the inactive state to a predetermined potential and to homogenize the two bit lines of a bit line pair with a common write/read amplifier. In this configuration, the predetermined potential is set by the two precharging transistors, while the bit lines are homogenized by an equalizer transistor.
Existing combined precharging and homogenizing circuits have a relatively large distance between the two bit lines, which can be attributed to the space requirement for the precharging transistors, the homogenizing transistor and possibly a leakage current limiter. Reducing the large distance between the bit lines represents a central problem for the desire to reduce the overall size of the memory cells.